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Author SHA1 Message Date
Quentin Carbonneaux
c9f04db881 refine assertion in liveness analysis 
We were redundantly checking cardinality in a
way that prevented fp regs from ever being
globally live.  We now check that the live
regs after a return are exactly the globally
live ones.
 2022-06-14 09:11:44 +02:00
Quentin Carbonneaux
9a3e131cf7 install in /usr/local by default 2022-05-12 11:36:25 +02:00
Quentin Carbonneaux
ee6c272416 tighten function definition spec 2022-05-12 09:24:23 +02:00
Quentin Carbonneaux
2c8697696d use an alias for \n in the il spec 2022-05-12 09:18:37 +02:00
Quentin Carbonneaux
ef68ab4066 avoid folding overflowing divisions 
Thanks to Paul Ouellette for reporting.
 2022-05-11 18:11:00 +02:00
Quentin Carbonneaux
fb742ec0e4 document spacing in il reference 2022-05-11 10:33:32 +02:00
Quentin Carbonneaux
6cd9797573 add installation notes 2022-05-10 12:02:36 +02:00
Michael Forney
4ac7d770d6 arm64: fix maximum immediate size for small loads/stores 
The maximum immediate size for 1, 2, 4, and 8 byte loads/stores is
4095, 8190, 16380, and 32760 respectively[0][1][2].

[0] https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRB--immediate-
[1] https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDRH--immediate-
[2] https://developer.arm.com/documentation/dui0802/a/A64-Data-Transfer-Instructions/LDR--immediate-
 2022-05-10 11:51:47 +02:00
Quentin Carbonneaux
2caa26e388 move nx stack annotation to gas.c 2022-04-11 14:57:50 +02:00
Daniel Xu
3c5cd9fdd0 Close input file after done reading 
Leaks resources to not close.

Signed-off-by: Daniel Xu <dxu@dxuuu.xyz>
 2022-04-11 14:39:01 +02:00
Quentin Carbonneaux
5f4b42abc7 do not leak type fields 
Thanks to Daniel Xu for reporting.
 2022-04-11 14:36:36 +02:00
Michael Forney
c6b41eb8c8 amd64: restore previous name of amd64_sysv target 2022-03-17 13:24:52 +01:00
Quentin Carbonneaux
bf2a90ef7c fix return for big aggregates 
The recent changes in arm and riscv
typclass() set ngp to 1 when a struct
is returned via a caller-provided
buffer.  This interacts bogusly with
selret() that ends up declaring a gp
register live when none is set in
the returning sequence.

The fix is simply to set cty to zero
(all registers dead) in case a caller-
provided buffer is used.
 2022-03-17 10:57:09 +01:00
Quentin Carbonneaux
cec9855fa0 detect target in tests 2022-03-15 22:34:03 +01:00
Quentin Carbonneaux
2416d29141 new -t? flag to print default target 2022-03-15 22:30:34 +01:00
Quentin Carbonneaux
da36b211ab homogenize riscv and arm abis 2022-03-15 14:18:31 +01:00
Quentin Carbonneaux
01142fa059 support env calls on arm64 
The x9 register is used for
the env parameter.
 2022-03-15 14:18:31 +01:00
Quentin Carbonneaux
c656c48f04 fix register count in riscv argregs 2022-03-15 14:18:23 +01:00
Quentin Carbonneaux
c5769f62b4 dynamic stack allocs for arm64 
I also moved some isel logic
that would have been repeated
a third time in util.c.
 2022-03-14 23:14:48 +01:00
Quentin Carbonneaux
329a18a30b add rv64/ to README 2022-03-14 15:32:46 +01:00
Quentin Carbonneaux
6ca9399ed6 output symbol type and size 
That is not available on osx
so I tweaked the gas.c api
a little to conditionally
output the two directives.
 2022-03-14 15:32:27 +01:00
Quentin Carbonneaux
7a7a5f4803 improve consistency in abis 2022-03-14 10:40:30 +01:00
Quentin Carbonneaux
905e9cef30 arm64/abi: fix big aggregates passed on the stack 
The riscv test abi8.ssa caught a bug
in the arm backend. It turns out we
were using the wrong class when loading
pointers to aggregates from the stack.

The fix is simple and mirrors what is
done in the riscv abi.
 2022-03-14 10:04:24 +01:00
Quentin Carbonneaux
c7842d84da dust off antique .tag 2022-03-11 13:38:46 +01:00
Quentin Carbonneaux
a9e4fa9715 rv64: plug holes in the abi 
Many things got fixed, but the most
notable change is the proper support
of floating point types in aggregates.

Minor fixes:
- selpar() did not deal correctly
  with Cfpint
- typclass() was reading out of
  bounds in the gp/fp arrays
- support for env calls
 2022-03-10 22:52:20 +01:00
Quentin Carbonneaux
e6debbbb02 two new tests in abi5.ssa 
They are meant to exercise the
hardware floating-point calling
convention of the risc-v target.
 2022-03-10 22:46:57 +01:00
Quentin Carbonneaux
7f7e34cd1f new abi stress test 2022-03-10 16:01:50 +01:00
Quentin Carbonneaux
9060981c10 flag types defined as unions 
The risc-v abi needs to know if a
type is defined as a union or not.

We cannot use nunion to obtain this
information because the risc-v abi
made the unfortunate decision of
treating

	union { int i; }

differently from

	int i;

So, instead, I introduce a single
bit flag 'isunion'.
 2022-03-08 15:57:06 +01:00
Quentin Carbonneaux
349794f3e4 cosmetics 2022-03-08 15:36:26 +01:00
lincoln auster [they/them]
3d294346ab doc: export function main in hello world example 
This enables the example to be compiled and run as-is, without any
additional modification.
 2022-03-07 15:34:28 +01:00
Quentin Carbonneaux
457e568ce9 rv64: formatting and bug fix in epilogue 2022-02-27 11:27:55 +01:00
Scott Graham
ddd101df66 doc: Add missing neg entry to index 2022-02-27 11:27:55 +01:00
Quentin Carbonneaux
c0cdef2e44 rv64: cosmetics in isel 2022-02-27 11:27:40 +01:00
Quentin Carbonneaux
65821c9b14 disable pie for rv64 tests 2022-02-25 10:51:22 +01:00
Quentin Carbonneaux
42cbdc04d0 improve consistency in arm64 and rv64 abis 2022-02-25 10:49:55 +01:00
Paul Ouellette
979385718b parse: allow string after first data item 2022-02-24 13:11:41 +01:00
Paul Ouellette
e04a2cd281 doc: minor fixes 2022-02-24 13:11:20 +01:00
Paul Ouellette
e7c13e8d01 fix folding of shifts of word operand by >32 2022-02-24 12:56:30 +01:00
Michael Forney
4e93eeaa3b add rv64 backend 
It is mostly complete, but still has a few ABI bugs when passing
floats in structs, or when structs are passed partly in register,
and partly on stack.
 2022-02-17 22:43:12 +01:00
Michael Forney
8e040d5861 test: add c[u]od checks to isel2 and add new integer compare test isel3 2022-02-17 22:35:22 +01:00
Michael Forney
2cba9f6871 cfg: remove unnecessary check for jump type 
This condition should match any jump with two successors. This is
needed on riscv64, where there is no flags register, so Jjnz is
used all the way to emit().
 2022-02-17 22:35:22 +01:00
Michael Forney
3b75357e2b Revert "skip jump arguments in rega" 
This reverts commit 028534d989.

riscv64 will have jump arguments with type RTmp.
 2022-02-17 22:35:22 +01:00
Michael Forney
630127c68b spill: consider jump argument as use of register 2022-02-17 22:35:22 +01:00
Quentin Carbonneaux
e092473be1 document the automatic use of bss 2022-02-11 09:14:17 +01:00
Michael Forney
7aceb24c50 gas: put zero data into .bss by default 
This allows frontends to use BSS generically, without knowledge of
platform-dependent details.
 2022-02-11 08:49:42 +01:00
Paul Ouellette
9fc0394d7e doc: fix name of export linkage flag 2022-02-11 08:45:32 +01:00
Quentin Carbonneaux
2ca6fb25a2 shared linkage logic for func/data 2022-02-02 21:09:37 +01:00
Quentin Carbonneaux
20ee522ce8 arm64: handle large slots in Ocopy 2022-01-31 16:57:22 +01:00
Detlef Riekenberg
a32ecfb452 Do not use the asm keyword as a local variable 
Signed-off-by: Detlef Riekenberg <wine.dev@web.de>
 2022-01-31 08:55:27 +01:00
Quentin Carbonneaux
f913cb0fb7 amd64/isel: nits 2022-01-28 11:10:34 +01:00