Commit graph

37 commits

Author SHA1 Message Date
Quentin Carbonneaux
40d0582ee0 add sign/zero extension operations 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
6dc9646f5e remove obsolete comment about MEM
It turned out to be not so useful to have a MEM
type for references.  Instead I used an OAddr
instruction that translates simply to a lea.
2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
7bbd361083 add the mul instruction 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
ca8c320dec replace RMem refs with an OAddr opertation 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
16fe5c1366 compile branches on and using test 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
bccfc34ca3 make sure eflags-writing do not disappear
This is a hack implementation, ideally I would like
something cleaner.  The problem is that regalloc thinks
an instruction is dead code because it's not aware that
it writes to eflags.
2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
67d3c2834d tentative support for fast allocs
It seems that the MEM reference type is
meaningless in too many positions.
Because of this, it is unclear if we
should keep it or just introduce a
OAddr instruction that only accepts
slots.

Regardless of the above, the spilling
module needs to use the new slot_()
function, also, the emit function needs
to fetch the size of the stack frame
from the slot[] array.

The naming is still very transitional,
here is a list of all bogus names I can
think of:

  - SLOT()
  - Tmp.spill
  - slot_
2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
5fc8104e00 major lifting: get rid of RReg
I've been septic since I introduced it, this commit
proves that it costs more than it helps.  I've also fixed
a bad bug in rega() where I alloc'ed the wrong size for
internal arrays.  Enums now have names so I can use them
to cast in gdb to get the name corresponding to a constant.
2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
78bf28f56e add basic support for stack allocation 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
8be35bf2be minor size optimization for 0XSet 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
7ce4d334e5 add a small size optimization to emit 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
1583f4bd32 split store into store{w,l} 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
f6df9e55c5 prefix register macros 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
ec5042148e fix my sloppy understanding of x86 assembly! 2015-09-15 23:01:31 -04:00
Quentin Carbonneaux
29c5f508b9 cosmetics 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
89039dcac1 movsb is not movsbl without suffix... 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
88d9573b76 attempt factoring store emission code 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
a69fe2c6c5 ugly support for store/load 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
e5c68a88ce simplify parsing 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
76bf96b268 add nmem to opdesc for use in the spiller
This new machine-independent mechanism might not be general
enough in the long term but, now, it provides a flexible way
to inform the spiller about the maximum number of arguments
of an instruction that can be spill locations.
2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
9966a181c1 add some load/store operations 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
a6bbd5c980 fix wrong instruction in emit 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
e65a615c90 jez becomes jnz, complete cmp+jmp contraction 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
7dc3e5dcf6 split cmp in two sizes 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
2482f4dbbb fix two bugs in isel 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
e5983ba1a2 fix 2 bad bugs in rega and improve substraction
The substraction contrained the register allocator
to allocate a different register for the result and
the second operand, now, we use a neg trick to compile
it down.  The machinery that was setup is, regardless,
interesting and will have to be used for floating
point computations (division).

The first bug in rega made broke the explicited loop
invariant:  we were using register allocation unavailable
information from other blocks.  It's still unclear
how we got wrong results from that considering mappings
are all 0-initialized.

The second bug is a stupid one, one sizeof operator was
missing from a memcpy...
2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
9c7b06d68f quick fix for comparisons with constants 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
246a48ba94 start work on comparisons
There are two things I overlooked so far.

1. Binary instructions like cmp that do not have a result
   in registers need the size suffix sometimes, for example
   when comparing a spill location with a constant.

2. The register allocator needs to be adapted to support the
   comparison instruction: it is not possible to compare two
   spill locations without using a register.
2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
1477dffe32 use cmp $0, it works with spill slots 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
6f2a7a245a adapt emit to new Ref setting 2015-09-15 23:01:30 -04:00
Quentin Carbonneaux
cf307002d9 start work on word/long handling 2015-09-15 23:01:29 -04:00
Quentin Carbonneaux
dff7044a2c replace IA with X for x64 instructions 2015-09-15 23:01:29 -04:00
Quentin Carbonneaux
0d5fb419e3 avoid keyword clash by using cons for constants 2015-09-15 23:01:29 -04:00
Quentin Carbonneaux
d8d17705c4 clean the commutativity + fix bug in emit
The commutativity information only makes sense for
arithmetic expressions.  To account for that, I introduced
a new tri-valued boolean type B3.  Memory operations, for
example, will receive an undefined commutativity trit.

The code emitter was buggy when rega emitted instructions
like 'rax = add 1, rax', this is now fixed using the
commutativity information (we rewrite it in 'rax = add
rax, 1').
2015-09-15 23:01:29 -04:00
Quentin Carbonneaux
92be2fdd17 start improving constants support 2015-09-15 23:01:29 -04:00
Quentin Carbonneaux
d8e40a56ec emit some x86-sepcific instructions 2015-09-15 23:01:29 -04:00
Quentin Carbonneaux
fd964388f7 add a code emitter for at&t syntax 2015-09-15 23:01:29 -04:00