Commit graph

25 commits

Author SHA1 Message Date
Quentin Carbonneaux
2c2051542b relax one assert
In this branch we only need that br[b->loop].b
is defined. This is the case if b->loop >= n.
2024-06-05 12:50:36 +02:00
Richard McCormack
c8fc20b8ef Eliminate fully overlapping blits after coalescing stack slots
I noticed that my compiler was generating redundant blits, and after
looking through the QBE debug output I believe that I found some low
hanging fruit to help clean them up.

I'm new to this codebase, so please treat this patch with a lot of
skepticism. Happy to make any changes.

Thanks for reviewing, and thank you for QBE!
2024-04-03 22:12:36 +02:00
Quentin Carbonneaux
498af259eb fix memory leak 2023-03-13 11:00:07 +01:00
Quentin Carbonneaux
f51aba22e0 refresh stale Tmp.link before use
During coalescing, the resizing/
reordering of the sl[] array
invalidates the indices stored
in the 'visit' field of temps;
we need to reset it before we
can use it again.
2023-03-13 10:51:41 +01:00
Quentin Carbonneaux
9632f2f148 kill dead stores when coalescing slots
This is necessary because, post
fusion, dead stores may clobber
data.  A new test case exposes
one such situation.
2023-03-11 21:51:10 +01:00
Quentin Carbonneaux
5e9726946d new UNDEF Ref
Crashing loads of uninitialized memory
proved to be a problem when implementing
unions using qbe.  This patch introduces
a new UNDEF Ref to represent data that is
known to be uninitialized.  Optimization
passes can make use of it to eliminate
some code.  In the last compilation stages,
UNDEF is treated as the constant 0xdeaddead.
2022-12-25 16:37:33 +01:00
Quentin Carbonneaux
26c1c30b7d new blit instruction 2022-12-14 23:18:26 +01:00
Quentin Carbonneaux
15e25a61b3 fix coalesce() to produce valid ssa
When multiple stack slots are coalesced
one 'alloc' instruction is kept in the il
and the other ones are removed and have
their uses replaced by the result of the
selected one. To produce valid ssa, it
must be ensured that the uses that get
replaced are dominated by the selected
'alloc' instruction. This patch ensures
dominance by moving the selected alloc up
in the start block as necessary.
2022-12-14 23:05:35 +01:00
Quentin Carbonneaux
c5ea06c136 treat retc as non-escaping
We may well treat all rets as
non-escaping since stack slots
are destroyed upon funcion
return.
2022-12-12 22:36:34 +01:00
Quentin Carbonneaux
2ec355df6a crash loads from uninitialized slots 2022-12-12 17:42:08 +01:00
Quentin Carbonneaux
7ee9970b32 renamings in coalesce() 2022-12-12 16:51:37 +01:00
Quentin Carbonneaux
b5da3f3d64 cosmetics in mem.c 2022-11-24 10:32:13 +01:00
Quentin Carbonneaux
04e2640901 rename Tmp.ins to be more descriptive 2022-11-22 21:55:06 +01:00
Quentin Carbonneaux
674901b718 new slot coalescing pass
This pass limits stack usage when
many small aggregates are allocated
on the stack. A fast liveness
analysis figures out which slots
interfere and the pass then fuses
slots that do not interfere. The
pass also kills stack slots that
are only ever assigned.

On the hare stdlib test suite, this
fusion pass managed to reduce the
total eligible slot bytes count
by 84%.

The slots considered for fusion
must not escape and not exceed
64 bytes in size.
2022-11-20 22:14:41 +01:00
Quentin Carbonneaux
f1c865f4bc more compiler warnings... 2018-04-26 22:59:30 +02:00
Emil Skoeldberg
e7a3875859 Fix compiler warnings.
Compiler warned about comparison between signed and unsigned values.
2018-04-26 22:49:36 +02:00
Quentin Carbonneaux
49a4593c33 prepare for multi-target
This big diff does multiple changes to allow
the addition of new targets to qbe.  The
changes are listed below in decreasing order
of impact.

1. Add a new Target structure.

To add support for a given target, one has to
implement all the members of the Target
structure.  All the source files where changed
to use this interface where needed.

2. Single out amd64-specific code.

In this commit, the amd64 target T_amd64_sysv
is the only target available, it is implemented
in the amd64/ directory.  All the non-static
items in this directory are prefixed with either
amd64_ or amd64_sysv (for items that are
specific to the System V ABI).

3. Centralize Ops information.

There is now a file 'ops.h' that must be used to
store all the available operations together with
their metadata.  The various targets will only
select what they need; but it is beneficial that
there is only *one* place to change to add a new
instruction.

One good side effect of this change is that any
operation 'xyz' in the IL now as a corresponding
'Oxyz' in the code.

4. Misc fixes.

One notable change is that instruction selection
now generates generic comparison operations and
the lowering to the target's comparisons is done
in the emitter.

GAS directives for data are the same for many
targets, so data emission was extracted in a
file 'gas.c'.

5. Modularize the Makefile.

The Makefile now has a list of C files that
are target-independent (SRC), and one list
of C files per target.  Each target can also
use its own 'all.h' header (for example to
define registers).
2017-04-08 21:56:20 -04:00
Quentin Carbonneaux
1bb7652484 deduplicate loadsz & storesz 2017-02-24 09:50:35 -05:00
Quentin Carbonneaux
f3301026fa reenable and fix a bug in memopt
While a minimal dead store elimination is not
implemented, the generated code looks quite a
bit better with them enabled.  It also is quite
cheap.
2017-02-24 09:50:28 -05:00
Quentin Carbonneaux
657c3fa66b match jumps/ops with il text 2016-04-20 09:56:29 -04:00
Quentin Carbonneaux
b8709501f9 do not rewrite overwritten slots in memopt 2016-04-18 13:25:32 -04:00
Quentin Carbonneaux
32d9e33191 harden memopt() 2016-04-13 09:53:50 -04:00
Quentin Carbonneaux
74562a93de reorder instructions 2016-04-04 14:45:49 -04:00
Quentin Carbonneaux
729aa97b79 cleanup error handling 2016-03-31 09:15:50 -04:00
Quentin Carbonneaux
b75cb8388f new layout, put LICENSE in root 2016-03-29 10:10:22 -04:00
Renamed from src/mem.c (Browse further)