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fix 2 bad bugs in rega and improve substraction

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The substraction contrained the register allocator
to allocate a different register for the result and
the second operand, now, we use a neg trick to compile
it down.  The machinery that was setup is, regardless,
interesting and will have to be used for floating
point computations (division).

The first bug in rega made broke the explicited loop
invariant:  we were using register allocation unavailable
information from other blocks.  It's still unclear
how we got wrong results from that considering mappings
are all 0-initialized.

The second bug is a stupid one, one sizeof operator was
missing from a memcpy...
This commit is contained in:
Quentin Carbonneaux 2015-08-05 21:46:15 -04:00
parent 7cb3e8587f
commit e5983ba1a2
3 changed files with 17 additions and 34 deletions
Download patch file Download diff file Expand all files Collapse all files

27
lisc/rega.c
View file

@ -102,8 +102,8 @@ rfree(RMap *m, int t)
BCLR(m->bt, t);
BCLR(m->br, r);
m->n--;
memmove(&m->t[i], &m->t[i+1], (m->n-i) * m->t[0]);
memmove(&m->r[i], &m->r[i+1], (m->n-i) * m->r[0]);
memmove(&m->t[i], &m->t[i+1], (m->n-i) * sizeof m->t[0]);
memmove(&m->r[i], &m->r[i+1], (m->n-i) * sizeof m->r[0]);
return r;
}
@ -293,11 +293,14 @@ rega(Fn *fn)
cur.n = 0;
cur.bt = (Bits){{0}};
cur.br = (Bits){{0}};
b1 = b->s1;
if (b1 && b->s2 && b->s2->loop > b1->loop)
b1 = b->s2;
if (b1 && b->loop > b1->loop)
b1 = 0;
b1 = 0;
if (b->s1 && b->s1->id > n) {
if (b->s1->loop > b->loop)
b1 = b->s1;
if (b->s2 && b->s2->id > n)
if (b->s2->loop > b1->loop)
b1 = b->s2;
}
/* try to reuse the register
* assignment of the most frequent
* successor
@ -362,18 +365,8 @@ rega(Fn *fn)
}
switch (rtype(i->arg[1])) {
case RTmp:
/* <arch>
* on Intel, we have to
* make sure we avoid the
* situation
* eax = sub ebx, eax
*/
if (opdesc[i->op].comm == F && r)
BSET(cur.br, r);
t = i->arg[1].val;
i->arg[1] = ralloc(&cur, t);
if (opdesc[i->op].comm == F && r)
BCLR(cur.br, r);
break;
case RReg:
BSET(cur.br, BASE(i->arg[1].val));