use a new Ref type for registers
This might not be a good idea, the problem was that many spurious registers would be added to the Bits data-structures during compilation (and would always remain 0). However, doing the above modification de-uniformizes the handling of temps and regs, this makes the code longer and not really nicer. Also, additional Bits structures are required to track the registers independently. Overall this might be a bad idea to revert.
This commit is contained in:
Quentin Carbonneaux
parent
93601b6d02
commit
9456200d91
9 changed files with 323 additions and 272 deletions
159
lisc/rega.c
159
lisc/rega.c
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@ -11,7 +11,7 @@ struct RMap {
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};
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extern Ins insb[NIns], *curi;
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static Sym *sym; /* symbol table in use */
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static Tmp *tmp; /* function temporaries */
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static struct {
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Ref src, dst;
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} *pm; /* parallel move constructed */
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@ -35,17 +35,23 @@ rref(RMap *m, int t)
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r = rfind(m, t);
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if (r == -1) {
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s = sym[t].spill;
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s = tmp[t].spill;
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assert(s && "should have spilled");
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return SLOT(s);
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} else
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return SYM(r);
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switch (tmp[t].type) {
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default:
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assert(!"invalid temporary");
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case TWord:
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return REG(LTW(r));
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case TLong:
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return REG(r);
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}
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}
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static void
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radd(RMap *m, int t, int r)
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{
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assert(sym[t].type == STmp && "invalid symbol");
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assert(RAX <= r && r < RAX + NReg && "invalid register");
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assert(!BGET(m->bt, t) && "temp has mapping");
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assert(!BGET(m->br, r) && "reg already allocated");
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@ -62,22 +68,19 @@ ralloc(RMap *m, int t)
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{
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int r;
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if (sym[t].type == SReg) {
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assert(BGET(m->br, t));
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r = t;
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} else if (BGET(m->bt, t)) {
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if (BGET(m->bt, t)) {
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r = rfind(m, t);
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assert(r > 0);
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assert(r != -1);
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} else {
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r = sym[t].hint;
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r = tmp[t].hint;
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if (r == -1 || BGET(m->br, r))
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for (r=RAX; BGET(m->br, r); r++)
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;
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radd(m, t, r);
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if (sym[t].hint == -1)
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sym[t].hint = r;
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if (tmp[t].hint == -1)
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tmp[t].hint = r;
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}
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return SYM(r);
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return REG(r);
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}
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static int
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@ -85,21 +88,16 @@ rfree(RMap *m, int t)
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{
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int i, r;
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if (sym[t].type == SReg) {
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assert(BGET(m->br, t));
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BCLR(m->br, t);
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return t;
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}
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if (!BGET(m->bt, t))
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return 0;
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return -1;
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for (i=0; m->t[i] != t; i++)
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assert(i+1 < m->n);
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r = m->r[i];
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BCLR(m->bt, t);
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BCLR(m->br, r);
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m->n--;
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memmove(&m->t[i], &m->t[i+1], (m->n-i) * sizeof(int));
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memmove(&m->r[i], &m->r[i+1], (m->n-i) * sizeof(int));
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memmove(&m->t[i], &m->t[i+1], (m->n-i) * m->t[0]);
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memmove(&m->r[i], &m->r[i+1], (m->n-i) * m->r[0]);
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return r;
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}
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@ -109,18 +107,12 @@ mdump(RMap *m)
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int i;
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for (i=0; i<m->n; i++)
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fprintf(stderr, " (%s, %s)",
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sym[m->t[i]].name,
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sym[m->r[i]].name);
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fprintf(stderr, " (%s, reg%d)",
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tmp[m->t[i]].name,
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m->r[i]);
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fprintf(stderr, "\n");
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}
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static inline int
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isreg(Ref r)
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{
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return rtype(r) == RSym && sym[r.val].type == SReg;
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}
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static void
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pmadd(Ref src, Ref dst)
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{
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@ -199,22 +191,25 @@ dopm(Blk *b, Ins *i, RMap *m)
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npm = 0;
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i1 = i+1;
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if (isreg(i->to))
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if (rtype(i->to) == RReg)
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for (;; i--) {
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r = i->to.val;
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rt = i->arg[0];
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assert(rtype(rt) == RSym);
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rfree(m, r);
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assert(rtype(rt) == RTmp);
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assert(BGET(m->br, r));
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/* todo, assert that r is not mapped */
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BCLR(m->br, r);
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rt = ralloc(m, rt.val);
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pmadd(rt, i->to);
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if (i==b->ins
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|| (i-1)->op!=OCopy
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|| !isreg((i-1)->to))
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|| rtype((i-1)->to) != RReg)
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break;
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}
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else if (isreg(i->arg[0]))
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else if (rtype(i->arg[0]) == RReg)
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for (;; i--) {
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r = i->arg[0].val;
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assert(req(i->to, R) || i->to.type == RTmp);
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if (req(i->to, R)) {
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if (BGET(m->br, r)) {
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for (n=0; m->r[n] != r; n++)
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@ -226,13 +221,13 @@ dopm(Blk *b, Ins *i, RMap *m)
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pmadd(rt, i->arg[0]);
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}
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} else if (BGET(m->bt, i->to.val)) {
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rt = SYM(rfree(m, i->to.val));
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rt = TMP(rfree(m, i->to.val));
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pmadd(i->arg[0], rt);
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}
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BSET(m->br, r);
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if (i==b->ins
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|| (i-1)->op!=OCopy
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|| !isreg((i-1)->arg[0]))
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|| rtype((i-1)->arg[0]) != RReg)
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break;
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}
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else
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@ -257,7 +252,7 @@ dopm(Blk *b, Ins *i, RMap *m)
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void
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rega(Fn *fn)
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{
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int n, t, u, r, x;
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int n, t, r, x;
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Blk *b, *b1, *s, ***ps, *blist;
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Ins *i;
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RMap *end, *beg, cur;
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@ -265,27 +260,23 @@ rega(Fn *fn)
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uint a;
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Ref src, dst;
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sym = fn->sym;
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tmp = fn->tmp;
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end = alloc(fn->ntmp * sizeof end[0]);
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beg = alloc(fn->ntmp * sizeof beg[0]);
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/* 1. gross hinting setup */
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for (t=Tmp0; t<fn->ntmp; t++)
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sym[t].hint = -1;
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for (b=fn->start; b; b=b->link) {
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for (i=b->ins; i-b->ins < b->nins; i++) {
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if (i->op == OCopy
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&& rtype(i->arg[0]) == RSym
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&& !req(i->to, R)) {
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t = i->arg[0].val;
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u = i->to.val;
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if (sym[t].type == SReg)
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sym[u].hint = t;
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if (sym[u].type == SReg)
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sym[t].hint = u;
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for (t=0; t<fn->ntmp; t++)
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tmp[t].hint = -1;
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for (b=fn->start; b; b=b->link)
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for (i=b->ins; i-b->ins < b->nins; i++)
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if (i->op == OCopy) {
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if (rtype(i->arg[0]) == RTmp
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&& rtype(i->to) == RReg)
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tmp[i->arg[0].val].hint = i->to.val;
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if (rtype(i->to) == RTmp
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&& rtype(i->arg[0]) == RReg)
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tmp[i->to.val].hint = i->arg[0].val;
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}
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}
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}
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/* 2. assign registers backwards */
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if (debug['R'])
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@ -305,36 +296,48 @@ rega(Fn *fn)
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* successor
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*/
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if (b1)
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for (t=Tmp0; t<fn->ntmp; t++)
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for (t=0; t<fn->ntmp; t++)
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if (BGET(b->out, t))
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if ((r = rfind(&beg[b1->id], t)) != -1)
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radd(&cur, t, r);
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for (x=0; x<2; x++)
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for (t=Tmp0; t<fn->ntmp; t++)
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if (x==1 || sym[t].hint!=-1)
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for (t=0; t<fn->ntmp; t++)
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if (x==1 || tmp[t].hint!=-1)
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if (BGET(b->out, t))
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if (!BGET(cur.bt, t))
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ralloc(&cur, t);
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/* process instructions */
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end[n] = cur;
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if (rtype(b->jmp.arg) == RSym)
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assert(rtype(b->jmp.arg) != RReg);
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if (rtype(b->jmp.arg) == RTmp)
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b->jmp.arg = ralloc(&cur, b->jmp.arg.val);
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for (i=&b->ins[b->nins]; i!=b->ins;) {
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i--;
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if (i->op == OCopy /* par. moves are special */
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&& (isreg(i->arg[0]) || isreg(i->to))) {
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&& (rtype(i->arg[0]) == RReg || rtype(i->to) == RReg)) {
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i = dopm(b, i, &cur);
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continue;
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}
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if (!req(i->to, R)) {
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switch (rtype(i->to)) {
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default:
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assert(!"unhandled destination");
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case RTmp:
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r = rfree(&cur, i->to.val);
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if (!r) {
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if (r == -1) {
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*i = (Ins){ONop, R, {R, R}};
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continue;
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}
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i->to = SYM(r);
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i->to = REG(r);
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break;
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case RReg:
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r = i->to.val;
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assert(BGET(cur.br, r));
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BCLR(cur.br, r);
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break;
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case -1:;
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}
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if (rtype(i->arg[0]) == RSym) {
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switch (rtype(i->arg[0])) {
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case RTmp:
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/* <arch>
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* on Intel, we attempt to
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* use the same register
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@ -342,11 +345,16 @@ rega(Fn *fn)
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* first argument
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*/
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t = i->arg[0].val;
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if (sym[t].hint == -1 && r)
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sym[t].hint = r;
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if (tmp[t].hint == -1 && r)
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tmp[t].hint = r;
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i->arg[0] = ralloc(&cur, t);
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break;
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case RReg:
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BSET(cur.br, i->arg[0].val);
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break;
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}
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if (rtype(i->arg[1]) == RSym) {
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switch (rtype(i->arg[1])) {
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case RTmp:
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/* <arch>
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* on Intel, we have to
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* make sure we avoid the
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@ -359,11 +367,15 @@ rega(Fn *fn)
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i->arg[1] = ralloc(&cur, t);
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if (opdesc[i->op].comm == F && r)
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BCLR(cur.br, r);
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break;
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case RReg:
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BSET(cur.br, i->arg[1].val);
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break;
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}
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}
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b->in = cur.bt;
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for (p=b->phi; p; p=p->link)
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if (rtype(p->to) == RSym)
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if (rtype(p->to) == RTmp)
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BCLR(b->in, p->to.val);
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beg[n] = cur;
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if (debug['R']) {
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@ -383,23 +395,22 @@ rega(Fn *fn)
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for (; (s=**ps); ps++) {
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npm = 0;
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for (p=s->phi; p; p=p->link) {
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assert(rtype(p->to) == RSlot
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|| rtype(p->to) == RSym);
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dst = p->to;
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if (rtype(dst) == RSym) {
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assert(rtype(dst)==RSlot|| rtype(dst)==RTmp);
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if (rtype(dst) == RTmp) {
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r = rfind(&beg[s->id], dst.val);
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if (!r)
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if (r == -1)
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continue;
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dst = SYM(r);
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dst = REG(r);
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}
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for (a=0; p->blk[a]!=b; a++)
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assert(a+1 < p->narg);
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src = p->arg[a];
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if (rtype(src) == RSym)
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if (rtype(src) == RTmp)
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src = rref(&end[b->id], src.val);
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pmadd(src, dst);
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}
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for (t=Tmp0; t<fn->ntmp; t++)
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for (t=0; t<fn->ntmp; t++)
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if (BGET(s->in, t)) {
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src = rref(&end[b->id], t);
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dst = rref(&beg[s->id], t);
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