201 lines
6.4 KiB
C
201 lines
6.4 KiB
C
/*
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* Copyright (C) 2012-2023 Free Software Foundation, Inc.
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*
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* This file is part of GNU lightning.
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*
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* GNU lightning is free software; you can redistribute it and/or modify it
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* under the terms of the GNU Lesser General Public License as published
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* by the Free Software Foundation; either version 3, or (at your option)
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* any later version.
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*
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* GNU lightning is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
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* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public
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* License for more details.
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*
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* Authors:
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* Paulo Cesar Pereira de Andrade
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*/
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#ifndef _jit_arm_h
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#define _jit_arm_h
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#define JIT_HASH_CONSTS 0
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#define JIT_NUM_OPERANDS 3
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/*
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* Types
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*/
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#define jit_swf_p() (jit_cpu.vfp == 0)
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#define jit_hardfp_p() jit_cpu.abi
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#define jit_ldrt_strt_p() jit_cpu.ldrt_strt
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#define jit_post_index_p() jit_cpu.post_index
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#define JIT_FP _R11
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typedef enum {
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#define jit_r(i) (_R4 + (i))
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#define jit_r_num() 3
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#define jit_v(i) (_R7 + (i))
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#define jit_v_num() 3
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#define jit_f(i) (jit_cpu.abi ? _D8 + ((i)<<1) : _D0 - ((i)<<1))
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#define jit_f_num() 8
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_R12, /* ip - temporary */
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#define JIT_R0 _R4
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#define JIT_R1 _R5
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#define JIT_R2 _R6
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_R4, /* r4 - variable */
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_R5, /* r5 - variable */
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_R6, /* r6 - variable */
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#define JIT_V0 _R7
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#define JIT_V1 _R8
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#define JIT_V2 _R9
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_R7, /* r7 - variable */
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_R8, /* r8 - variable */
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_R9, /* r9 - variable */
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_R10, /* sl - stack limit */
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_R11, /* fp - frame pointer */
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_R13, /* sp - stack pointer */
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_R14, /* lr - link register */
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_R15, /* pc - program counter */
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_R3, /* r3 - argument/result */
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_R2, /* r2 - argument/result */
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_R1, /* r1 - argument/result */
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_R0, /* r0 - argument/result */
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#define JIT_F0 (jit_hardfp_p() ? _D8 : _D0)
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#define JIT_F1 (jit_hardfp_p() ? _D9 : _D1)
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#define JIT_F2 (jit_hardfp_p() ? _D10 : _D2)
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#define JIT_F3 (jit_hardfp_p() ? _D11 : _D3)
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#define JIT_F4 (jit_hardfp_p() ? _D12 : _D4)
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#define JIT_F5 (jit_hardfp_p() ? _D13 : _D5)
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#define JIT_F6 (jit_hardfp_p() ? _D14 : _D6)
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#define JIT_F7 (jit_hardfp_p() ? _D15 : _D7)
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_S16, _D8 = _S16, _Q4 = _D8,
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_S17,
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_S18, _D9 = _S18,
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_S19,
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_S20, _D10 = _S20, _Q5 = _D10,
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_S21,
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_S22, _D11 = _S22,
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_S23,
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_S24, _D12 = _S24, _Q6 = _D12,
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_S25,
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_S26, _D13 = _S26,
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_S27,
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_S28, _D14 = _S28, _Q7 = _D14,
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_S29,
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_S30, _D15 = _S30,
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_S31,
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_S15,
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_S14, _D7 = _S14,
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_S13,
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_S12, _D6 = _S12, _Q3 = _D6,
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_S11,
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_S10, _D5 = _S10,
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_S9,
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_S8, _D4 = _S8, _Q2 = _D4,
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_S7,
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_S6, _D3 = _S6,
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_S5,
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_S4, _D2 = _S4, _Q1 = _D2,
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_S3,
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_S2, _D1 = _S2,
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_S1,
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_S0, _D0 = _S0, _Q0 = _D0,
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_NOREG,
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#define JIT_NOREG _NOREG
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} jit_reg_t;
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typedef struct {
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jit_uint32_t version : 4;
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/* this field originally was only used for the 'e' in armv5te.
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* it can also be used to force hardware division, if setting
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* version to 7, telling it is armv7r or better. */
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jit_uint32_t extend : 1;
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/* only generate thumb instructions for thumb2 */
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jit_uint32_t thumb : 1;
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jit_uint32_t vfp : 3;
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jit_uint32_t neon : 1;
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jit_uint32_t abi : 2;
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/* use strt+offset instead of str.w?
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* on special cases it causes a SIGILL at least on qemu, probably
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* due to some memory ordering constraint not being respected, so,
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* disable by default */
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jit_uint32_t ldrt_strt : 1;
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/* assume functions called never match jit instruction set?
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* that is libc, gmp, mpfr, etc functions are in thumb mode and jit
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* is in arm mode, or the reverse, what may cause a crash upon return
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* of that function if generating jit for a relative jump.
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*/
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/* Apparently a qemu 8.1.3 and possibly others bug, that treat
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* ldrT Rt, [Rn, #+-<immN>]! and ldrT Rt, [Rn], #+/-<immN>
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* identically, as a pre-index but the second one should adjust
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* Rn after the load.
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* The syntax for only offseting is ldrT Rt{, [Rn, #+/-<immN>}]
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*/
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jit_uint32_t post_index : 1;
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jit_uint32_t exchange : 1;
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/* By default assume cannot load unaligned data.
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* A3.2.1
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* Unaligned data access
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* An ARMv7 implementation must support unaligned data accesses by
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* some load and store instructions, as Table A3-1 shows. Software
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* can set the SCTLR.A bit to control whether a misaligned access by
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* one of these instructions causes an Alignment fault Data Abort
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* exception.
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* Table A3-1 Alignment requirements of load/store instructions
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* Result if check fails when
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* Instructions Alignment check SCTLR.A is 0 SCTLR.A is 1
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* LDRB, LDREXB,
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* LDRBT, LDRSB,
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* LDRSBT, STRB,
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* STREXB, STRBT,
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* SWPB, TBB None - -
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* LDRH, LDRHT,
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* LDRSH, LDRSHT,
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* STRH, STRHT,
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* TBH Halfword Unaligned access Alignment fault
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* LDREXH, STREXH Halfword Alignment fault Alignment fault
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* LDR, LDRT,
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* STR, STRT Word Unaligned access Alignment fault
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* LDREX, STREX Word Alignment fault Alignment fault
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* LDREXD, STREXD Doubleword Alignment fault Alignment fault
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* All forms of
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* LDM and STM,
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* LDRD, RFE, SRS,
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* STRD, SWP Word Alignment fault Alignment fault
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* LDC, LDC2,
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* STC, STC2 Word Alignment fault Alignment fault
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* VLDM, VLDR,
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* VPOP, VPUSH,
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* VSTM, VSTR Word Alignment fault Alignment fault
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* VLD1, VLD2,
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* VLD3, VLD4,
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* VST1, VST2,
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* VST3, VST4,
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* all with
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* standard
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* alignment (a) Element size Unaligned access Alignment fault
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* VLD1, VLD2,
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* VLD3, VLD4,
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* VST1, VST2,
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* VST3, VST4,
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* all with
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* @<align>
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* specified (a) As specified by Alignment fault Alignment fault
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* @<align>
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*
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* (a) These element and structure load/store instructions are only in
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* the Advanced SIMD Extension to the ARMv7 ARM and Thumb instruction
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* sets. ARMv7 does not support the pre-ARMv6 alignment model, so
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* software cannot use that model with these instructions.
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*/
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jit_uint32_t unaligned : 1;
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jit_uint32_t vfp_unaligned : 1;
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} jit_cpu_t;
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/*
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* Initialization
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*/
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extern jit_cpu_t jit_cpu;
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#endif /* _jit_arm_h */
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